1. Field
Example embodiments relate generally to a data training system and method thereof.
2. Description
Data training may regulate skew generated during a read operation reading data from a memory device (e.g., a dynamic random access memory (DRAM)) and/or during a write operation writing data to the memory device. Data training may test a memory device with a memory controller by applying a given data pattern to the memory device and regulating the skew of each data pin based on a data pattern received back from the memory device.
FIG. 1 is a flowchart illustrating a conventional data training process.
Referring to FIG. 1, a data pin for executing data training may be selected (at S1000). A delay time i of a record data pattern may be initialized (e.g., to a minimum value) (at S1010). The given data pattern may be recorded or written in a memory cell and the recorded data pattern may then be read from the memory cell (at S1020). Next, the recorded data pattern and the read data pattern may be compared to determine whether the compared data patterns are the same (at S1030).
If the compared data patterns are determined to be the same, i may be incremented by one (e.g., or another value corresponding to 1/N of a clock cycle of a given clock signal) (at S1040) and the process returns to S1020. Otherwise, if the compared data patterns are determined not to be the same, the current delay time t_err (e.g., the value of i when the inequality is determined) may be stored (at S1050). Next, the delay time i may be compared with a threshold delay time t_max (at S1060). In an example, the threshold time t_max may correspond to a clock cycle of a given clock signal.
Referring to FIG. 1, if the delay time i is determined to be less than the threshold delay time t_max, the delay time i may be incremented (at S1040) and the process may return to S1020. Otherwise, if the delay time i is determined not to be less than the threshold delay time t_max, a given data delay time for reducing skew may be determined (at S1070) based on the delay time t_err. The process of FIG. 1 may then determine whether the above-described process has been applied to each data pin (at S1080). If at least one data pin is determined not to have been tested (e.g., to determine a sufficient delay time to reduce skew) (in S1080), one of the non-tested data pins may be selected (at S1090) and the process returns to step S1010. Otherwise, If each data pin is determined to have been tested, the process of FIG. 1 may terminate.
Accordingly, the difference between skews of each data pin may be estimated. A time margin of the data and the clock signal may be increased by the controller setting the delay time which may reduce the skews of each data pin, which likewise may reduce an occurrence of data errors.
However, the conventional process of FIG. 1 may not applied if data is already present in an entirety of a given memory cell (e.g., because the test pattern would otherwise overwrite the data). Also, the conventional process of FIG. 1 may consume a relatively large amount of time to perform. Further, the complexity of the conventional process of FIG. 1 may increase as the number of functions of the controller increases. Also, the conventional process of FIG. 1 may not allow a memory device to directly detect a data error, and the size of the memory device performing the conventional process of FIG. 1 may increase if a resistor for separate data training is used.